Abstract

A Software Defined Radio (SDR) is a transmitter and receiver system that uses digital signal processing (DSP) for\ncoding, decoding, modulating, and demodulating data. This paper presents the framework for hardware implementation of\nSDR using Orthogonal Frequency Division Multiplexing (OFDM). The framework comprises of VLSI mapping of\nalgorithms, Orthogonal Frequency Division Multiplexing (OFDM), Quadrature Phase Shift Keying (QPSK), Fast Fourier\nTransform (FFT) Algorithms and most importantly, the algorithm for Direct Digital Frequency Synthesis (DDFS). A digital\nfrequency synthesizer with optimized time and area resources has been proposed for the SDR. This VLSI implementation of\nthe DDFS computes the sine and cosine function on a single edge of clock, thus proving to be optimized in terms of area and\nspeed. Fixed-Point implementation was accomplished with ModelSim simulator. Verilog HDL was used as a description\nlanguage for mapping Algorithms in VLSI. Xilinx Spartan 3 XC3S200 Field Programmable Gate Array (FPGA) was chosen\nas a Hardware Platform for the System Implementation.