A Comparative Analysis of Vernier Delay Line TDC based on Resolution, Area, Power and Conversion Time

Conference: McGraw-Hill International Conference on Signal, Image Processing Communication and Automation
Author(s): Shreesha S, Mahaveera K Year: 2017
Grenze ID: 02.MH-ICSIPCA.2017.1.16 Page: 97-106

Abstract

Time to Digital Converters (TDC) are devices used to identify an event. TDCs can also be used to measure time\ninterval between two events. One of the key components of All Digital Phase Locked Loop (ADPLL) is TDC. ADPLLs are\nused in applications such as Bluetooth, Wi-Fi and GSM. An attempt is made to compare Vernier Delay Line (VDL) TDC\nusing Symmetric SR Latch, VDL TDC using Simplified SR Latch and VDL TDC using Simplified Sampler. The results are\ncompared on the basis of Resolution, Area, Power and Conversion Time. The VDL TDC architectures having 19 stages are\nimplemented in Cadence virtuoso gpdk 45 nm technology with a supply voltage of 1.2 V. All the implemented VDL\narchitectures produce a same resolution of 2 ps at 1 GHz input frequency. VDL TDC using Symmetric SR Latch consumes\n722 transistors, 5.792 mW of power and 1.0175 ns of conversion time. VDL TDC using Simplified SR Latch consumes 570\ntransistors, 3.385 mW of power and 1.0609 ns of conversion time. Similarly, VDL TDC using Simplified Sampler consumes\n532 transistors, 4.929 mW of power and 497.4 ps of conversion time. The simulation results show that VDL TDC using\nSimplified Sampler is more efficient in terms of area and conversion time.

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MH-ICSIPCA - 2017