Design and Performance Analysis of 20nm 7-Fin SOI FinFET

Conference: International Conference on Soft Computing Applications in Wireless Communication
Author(s): Gurleen Kaur, Gurpurneet Kaur, Manpreet Singh Brar Year: 2017
Grenze ID: 02.SCAWC.2017.1.518 Page: 252-255


Scaling of standard CMOS is becoming difficult due to rising subthreshold leakage and gate leakage. FinFETs i.e.\nMulti-gate FETs have come out as the most assuring contenders to extend the scaling of CMOS insub-25nm region this is\nbecause of more electrostatic control due to use of multiple gatesover the channel which lowers the coupling between drain\nand source in the subthreshold regime. Driving capability is increased for low voltage designs by using SOI FinFETs. In this\npaper, designing and performance analysis in terms of V-I characteristics of 20nm 7-fin SOI FinFET is discussed.


SCAWC - 2017