Abstract

In this paper a novel architecture for DWT computation of input image of size greater than 512 x 512 is\ndesigned and implemented on FPGA. DWT offer better subjective image quality compared to Discrete Cosine\nTransform (DCT)-based compressed images under low bit rates, due to DWT’s inherent scalability and better decorrelation\nproperties. DWT has traditionally been implemented by convolution or FIR filter bank structures. Such\nimplementations require both a large number of arithmetic computations and a large storage features that doesn’t\nsupport high speed or low power image or video processing applications. So a scheme called “Lifting Based\nDWT” is proposed which requires far fewer computations than the previous methods. The proposed architecture is\nimplemented on XC3S500e-5fg320 FPGA and is operated at a maximum frequency of over 231.192 MHz and\nconsumes area less than 30% of the CLB resources on FPGA.