Optimization of Low Power Adder Cells using 90 NM TG Technology

Conference: Sixth International Conference on Advances in Power Electronics and Instrumentation Engineering
Author(s): Nitasha Jaura, Balraj Singh Sidhu Year: 2015
Grenze ID: 02.PEIE.2015.6.505 Page: 11-20

Abstract

Continuous scaling of the transistor size and reduction of the operating voltage has led to a significant performance improvement of integrated circuits (ICs). Lower power consumption and smaller area are the most important criterion for the fabrication of Digital Signal Processing (DSP) systems and high performance systems like Laptop and Android based applications in order to achieve the best performance with minimized power consumption. In the proposed paper the average power dissipation, transistor count and propagation delay signals have been minimized as the length and width of NMOS and PMOS transistors are optimized. The proposed circuits are designed and optimized using the Transmission Gate (TG) technology, and the comparative performance analysis of these TG based three different 8-bit adders named, Ripple Carry Adder, Carry Look-ahead adder and Carry Bypass Adder has been carried out with 90 nm technology, using TANNER EDA tool.

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PEIE - 2015