HDL Design for BIST based IEEE Boundary Scan SOC Array Scanner Archtecture using FPGA
Conference: Sixth International Conference on Recent Trends in Information, Telecommunication and Computing
AbstractThe Aim is for Design Implementation Of IEEE 1149.1 Standard Based Boundary Scan B.I.S.TArray SOC Architecture for Testing of Multiple SOC’s at a time for flexibility and compatibility. This DesignConsists Of Array Of BIST Modules Parallel. Testing Done Parallel by using these BIST Modules. “This isSimply a Parallel Test Computing Technique – Universal SOC Tester”. The Process Of Design Implementedthrough VHDL and / Verilog HDL. Simulation and Synthesis Done By Xilinx ISE 9.2 i EDA Software DesignTool. Programming and Debugging Done By FPGA SPARTAN-III. |
ITC - 2015
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