HDL Design for Ultra High Multi Frequency Clock Ratemulti Channel PRBS Universal Data Scrambler Descrambler ASIC IP Core
Conference: Sixth International Conference on Recent Trends in Information, Telecommunication and Computing
AbstractScrambler De-Scrambler is a device used to encode and decode the message data in to randomized(Seed words) data.. This paper deals Design of High Speed Multichannel Universal Data Scrambler De-ScramblerOf Different Data Rates (Giga/Tera Bit Rate) for Ultra High Speed Wireless Applications like Gigabit WIMAX,WIFI,3G,4G,Parallel Data Computing, Internet, Cloud Computing etc. Scrambling Different PRBS Data as perCCITT – ITU Standards. This Design consists of Different Pattern Sequence based PRBS Generators and XOR Gates for encryption and decryption of digital data either serially/parallel. Design using Xilinx ISE 9.2i Software,Programming done by using VHDL and Verilog HDL, Design Implementation on Latest Xilinx Spartan III FPGA Kit. |
ITC - 2015 |